Here, QA, QB, QC, and QD are data outputs. The second flip flops output ‘QB’ is connected to the third flip flops input DC, and the third flip flops output ‘QC’ is connected to the fourth flip flops input ‘DD. In the diagram, the first flip flop output ‘QA’ is connected to the second flip flop input ‘DB’. The construction of the SIPO shift register is shown above.
The operation of this shift register is, first all the flip flops from the circuit from FF1 to FF4 have to RESET so that all the outputs of FFs like QA to QD will be at logic zero level so there is no parallel data output. The 4-bit SIPO shift register circuit is shown below. The working of the SIPO shift register is that it takes the serial data input from the first flip flop of the left side and generates a parallel data output. SIPO Shift Register Diagram Working of SIPO Shift Register
